Binary code synchronizer



7 Sheets-Sheet 4 Filed May 5, 1958 FS mv AAS AUV S S INV ENTOR.

6501265 F.' GROND/N Feb. 28, 1961 G. F. GRONDIN 2,973,407

BINARY CODE sYNcHRoNIzER Filed May 5, 1958 TSheets-Sheet 5 Feb. 28, 1961G. F. GRoNDlN 2,973,407

BINARY come: sYNcHRoNIzER Filed May 5. 1958 'r sheets-sheet e INVENTOR.Genes-E F. Geo/vo//v BY7 2 Q g QTTOBNEYS Feb. 28, 1.961 G. F. GRONDIN2,973,407

BINARY CODE SYNCHRONIZER Filed May 5, 1958 '7 Sheets-Sheet '7 INVENTOR;

GEORGE l-T GeoND/N BYMM;

2,973,401 srNAnY coton' sYNcHaoNiznn George F. Grondin, Van Nuys,Calif., assigner to Collins Radio Company, Cedar Rapids, iowa, acorporation of iowa naar May' s, 195s, ser. Ne. 'rashes 19 claims. (ci.irs-'no rhis invention relates to means for translating nonsynchronouspulse-coded information into synchronous bit form.

Many types of pulse-coded Amodulation are feasible. One commonly usedtype is found inthe teletypewriter art. This type, for example, can useinformation code characters having tive binary-coded bauds. Also, twoadditional bauds, called a Start baud and a stop baud, are used tospecify the beginning and end of a code character. Thus, a seven baudcharacter has been specified, and it is used in an exemplary fashionthroughout this specification. `Code characters of other sizes can alsobe used. 4, K n

Conventionally, the start and iive information bauds have equaltime-length; while the stop baud has approximately 1.41 times the lengthof any of the other bauds. Accordingly, the output of conventionalteletypewritercoding devices is nonsynchronous with respect to baudtiming.

The invention can receive nonsynchronons data and changes it into baudsynchronous data in preparation for synchronous data transmission. Abaud synchronous transmission can consume less bandwith and can euablereception with a higher signal-to-noise ratio than a nonsynchronoustransmission of data. Synchronous transmission requires that allbaudsthave the same length or an integer multiple of a given length.

Other nonsynchronous-to-synchronous code converters are known. Forexample, a previous converter is described and claims in my prior PatentNo. 2,838,858, tiled February 28, 1956, titled Code Converter andassigned to the Collins Radio Company. in my prior system,

parallelstorage means was providedl for each information baud, with thestorage being for a period of several bauds. A timing source was used tosynchronously sample the storage means in a given order. The synchronoustiming rate was necessarily faster than the instantaneous input rate;and, accordingly, the system occasionally provided a blank characteroutput While the norsynchrouous input data caught up with thesynchronous readout.

In my present system an entirely different principle is used; whichenables structural simplification with resulting economies, as Well asan improvement in performance. tionship between received nonsynchronousdata and interleaved synchronous-timing pulses. A decision functionin'the invention uses this phase relationship to decide whether or notto directly sample the nonsynchronous data. f certain timing'pulses arephased with the introductory portion of the nonsynchronous data, thedecision is to sample directly.A phased, the decision is not to sampledirectly,'but` instead to sample the data from a series-storage device,which simply delays the incomingdata by a fraction of a baud period.

The

for sampling purposes, because that portion usually has The presentinvention determines the phase relalf other timing pulses are so.

central fifty-percent portion ofy each received nonsynchronous baud isgenerally'its mosereliable portion,

" 12,973,407 Patented Feb. 28, 1961 rate is either instantaneouslyfaster or slower than the synchronous output rate.

It is another object of this inventionto provide a code` converter thatdoes not have any mechanically moving parts.

code converter that is bistable in operation and thus has bistablereliability.

it is a further object of this invention to provide a binary codeconverter which is more simple in its structure thanany prior converterknown, and is thus more economical to manufacture. f Further objects,features, and advantages of this tion will become apparent to oneskilled inthe art upon further study of this specification and drawings,in which; Figures 1 and 2 illustrate basic baud-timing diagrams; Figure3 illustrates the basic system used by the invention;

Figures 5(A)7 (B), (C), (D), (E), (F), and (G) illustrate timingdiagrams;

Figure 6 illustrates another detailed form of tion;

the inven- Figure 7 gives waveforms used in explaining theI opera-Kltion ofthe invention in Figure 6; and, l l y t Figures 8 and 9 representtrigger circuit arrangements which, among others, can be utilized intheinvention.

Now referring to the drawings for a more thorough explanation of theinvention, Figures l andv 2 show timing relationships that illustratebasic principles usedby the. A teletypewriter code-character isillustrated,

invention. in Figure l(A), which is defined as being nonsynchronous asto its starting time. That is, the initiation ojfitsfstart v` pulse israndom with respect to any synchronous wave source, such as synchronouspulses-B shown in Figure.

l(C). The character is bounded by start and stopbauds, and between themare five information bauds, designated as l, 2, 3, 4 and 5, which areofi-on pulsecoded in the conventional manner. Hence, information baudsl-5 are binary in form, and each may be either a mark or a space. A markherein implies an electrical quantity substantially filling therespective portions of' thebaud,l and a space implies the absence'offany(or a different valued) electrical quantity in the baud spaeef.Generally, the terminating stop baudv is 4a. Space` .so thatyimmediately upon its termination, a new code character can be initiated.v y

Figure l(B) illustrates the same character as in Figure l(A) but delayedby one-half the period of thefstart. baud. For initial simplicity, thelength of thestart and,

information bauds in Figures 1(A) and (B) areassunied to be equal to theperiod of synchronous-timing puiSsEj However, the stop pulse has alength of approximately. 1.4 times the period of the other bauds in thecode char#v acter and prevents a sequence of such code characters frombeing synchronous.

In practice, ideal rectangularly-shaped pulses are seldom found. 'theusual pulse has a rounded top;l and sloping rise and fall portions.Consequently, its best pon. tion for reliably determining its polarityAis its., center poo. tion. The central fifty percent portionsarejsampled in.; the illustrated embodiments, with the' exception of.thej

stopi bauds, which are sampled in the eighteen to tittycode converterwhich changes nonsynchronous binary data to, synchronous data althoughthe received nonsynchronous- It is still another object of thisinvention tqprovide a Figure 4 shows a more detailed form oftheinvention;v

three percent portions from their leading edge. This however provides asampling time range with the same spacing from the leading edge for thestop baud as for the other bauds. In Figures l(A) and 1(13) the samplingranges are illustrated as 16, 11, 12, t3, 14, 15 and 16.

Sampling in the invention is done by synchronous pulses-B. The dutycycle of synchronous pulses-B is very small; wherein the pulse durationis very short compared to a baud period.

f It can be viewed in Figures l(A) and (B) that the middle fty percentsampling ranges of the direct and stored inputs are complementary. Thatis, one set of ranges exists during times when the other does not exist.It then is realized that the timing of pulses-B will occur within'eitherthe sampling range of the direct input or of the stored input,regardless of the random phasing of the nonsynchronous input.

vA decision operation is used in the invention to Vdetermine whether thedirect input or stored input has a set of sampling ranges during whichpulses-B occur.

For simplicity in Figure l(A), the baud periods, except for the stopbaud, were presumed to have a period equal to that of the synchronouspulses. Hence, it is the incongruous length of the stop baud whichprevented synchronism for a sequence of code characters.

Figures 2(C) and (D) illustrate conditions Where all bauds havenonsynchronous periods. Figure 2(A), however, is the same as Figure l(A)and is provided again for comparison purposes. Figure 2(B) illustrates arelative timing for synchronous pulses-B. Figure 2(C) illustrates anonsynchronous code-character transmitted at a faster rate than thecharacter of Figure 2(A), while the nonsynchronous character in Figure2(D) is shown at a slower rate. Each of the code characters in Figures2(A), (C) and (D) is assumed to start at the same time 18, illustratedby a common verticalline 1S. The timing of the synchronous pulse inFigure 2(8) is carried to Figures 2(A), (C) and (D) by vertical dashedlines 21-26. With the fast code character of Figure 2(C), the baudsampling ranges advance with respect to the synchronous-timing pulses.On the other hand, with the slow character of Figure 2(D), the samplingranges retard with respect to the synchronous-timing pulses.

The extremeness of the cases in Figures 2(C) and (D) can now berealized. Accordingly, it is noted in each case when lirst timing pulse21 falls centrally in the start baud, sixth pulse 26 falls on oppositeboundaries of sampling ranges 15 in Figures 2(C) and (D). Althoughtiming pulses occurring during the stop bauds will be slightly outsidestop-baud range i6, given in Figure 1(A), no harm is done sincegenerally the stop baud is the absence of a pulse. The cases in Figures2(C) and (D) are predicted upon fifty percent central sampling ranges.They permit a rate`variation for the nonsynchronous input of about plusor minus ve percent from the synchronous timing rate. However, where thenonsynchronous pulses are reasonably Well formed, the invention canaccept more extreme nonsynchronous rates.

Figure 3 illustrates a basic form of the invention. Nonsynchronous datais received at an input terminal 3d, and is provided to three places inthe system by leads 3l, 32 and 33, which respectively connect to aswitching means 36, a storage delay device 37 and a decision device 38.`Storage device 37 delays the data by approximately one-half baud period,so that the data on its output lead 39 is about one-half baud periodbehind the direct data on lead 31. Storage device 37 can be a bistabledevice or a delay line. The latter is assumed in Figure l.

In order to assist the decision function of the system, a second set ofsynchronous pulses is provided at a terminal 3S and is designated aspulses-A. Pulses-A occur onehalf of a synchronous period from pulses-B.Their interleaved-time relationship can be seen by viewing Figures 5 (C)and (D). Deville. 33 receives pulses A and B from terminals 35 and 46.It observes whether a pulse-A or a pulse-B occurs during the fiftypercent midlrange period of each start pulse. If a pulse-A is thenobserved, the delayed data is sampled, because then sampling pulses-Bwill occur within (or very close to) the fty percent mid-portions of thehalf-baud delayed data. On the other hand, if a pulse-B is observedduring the start pulses fiftypercent mid-range period, the direct datais sampled, since sampling pulses-B then occur during (or very near to)the fty percent mid-portionsk of the direct data.

Switching means 36 receives inputs from the direct data of lead 31 andthe stored data of lead 39. Switching means 36 operates like adouble-throw switch. Although its output 40 can normally be connected toeither input, `it preferably is normally connected to the stored inputas shown in Figure l. Hence, switching to the direct input only occurswhen decision device 38 sees a pulse-A during the first one-quarterperiod of a start baud.

The reason why a decision is made during the start baud rather thanduring some other baud is that a codecharacter timing change is firstsensed with its start baud; and a decision made then holds for theremaining bauds of its character.

A read-out sampling gate 43 receives the selected output of switchingmeans 36 and samples portions of that output only during the shortdurations of Synchronous pulses-B,'which are provided as an input tosampling gate circuit 43 from a terminal 46. Thus, gate 43 is opened forshort synchronous periods that occur during the fifty percent midrangesof data received by it. Accordingly, gate 43 provides synchronous outputpulses which have a polarity dependent upon the sampled data pulses. Areadout bistable circuit 4-4 is triggered by and to a correspondingpolarity as the synchronous sample pulses from gate 43 to providesynchronous output data at terminal 45.

Another form of the invention is illustrated in Figure 4 which generallyoperates in the same manner as the embodiment of Figure 3. It alsoaccepts nonsynchronous data at terminal 30 andvprovides synchronousoutput data at terminal 45. The component blocks delined in Figure 3 areillustrated by broken lines in Figure 4 but are given the same referencenumbers. Storage device 37 includes a gate 51 and a {lip-flop or triggercircuit 56. Gate 51 has an enabling input S2 connected to data inputlead 32, and has another input 53 connected to terminal 35 to receivesynchronouswtiming pulses-A. Thus, gate 51 synchronously samples thedirect data at the instances of pulses-A. Circuit 56 is connected to theoutput of gate Si, and is triggered to a voltage state corresponding tothe polarity state of the data synchronously sampled by gate 51. Thatis, Hip-flop S6 is synchonously actuated by the output of gate Si to thesame state as the received data.

Since there is assumed to be a random phase relationship between theinput data and the synchronous-timing pulses, the sampling of the databy gate 5l can be from any portion of the bauds of the nonsynchronousdata, and not necessarily from their tifty percent midranges. It will beseen later in this specification that the output of trigger circuit 56is used only when the iifty percent midranges (or very nearlyV so) ofthe data bauds are sampled by gate 51 because of the operation ofdecision anregend merely provides. isolation between the outputs 'ofgates 62 and 63.

Decision device 3d receives the nonsynchronous input data from lead 33at a delay means 71, which provides an approximate one-quarter bauddelay. rIhus, when the leading edge of a start pulse is received atnonsynchronous input terminal 3o, delay means 71 provides an outputpulse one-quarter baud later, hereafter called a delayed-start pulse.

The delayed-start pulse is received at an input 91 of a binary-countersystem 7i). Counter system 70 is started by the delayed-start pulse tosynchronously count the number of bauds in the received character, whichhere is seven. Counter system 79 disables decision d..- vice 38 fromterminal 3i) during the remaining part of the character, so that adecision is made only once per character, which is at its beginning.Hence, noise and other bauds during the remaining part of the characterdo not interfere with the decision operation.

Counter system 7i) comprises four tandem-connected binary counters,which can be ip-iiop circuits. Each of the four counters is capable ofsimultaneously providing two opposite output states, well known for aflip-flop circuit; wherein either output can have one of two voltagelevels a or b. However, with counters #1, #2 and #4, only one output isused; while with counter #3 both outputs 1 and 2 are used. The countersare connected in a pulse-divider arrangement, wherein the counting inputof counter system 7@ is input 92 of counter #1.

Synchronous pulses-A from terminal are provided to counter input 92through a gate 72, that has an enabling input '75 connected to theoutput of counter #4. Accordingly, gate '72 is enabled to pass pulses-Awhen counter #4 provides an output level b.

Furthermore, when counter #4 input 9i receives a delayed-start pulse, ittriggers the counter #4 output to level b, which creates a leading edgethat directly triggers counter #l input 92, as gate 72 is beingsimultaneously enabled to pass the next seven pulses-A.

Upon receipt of the seventh pulse-A, the output of counter #4 istriggered back to level "a which disables gate 72 and stops furtherpulses-A from reaching the counter. At that time, the code-character hasended, and counter #i4 is again triggerable by the next delayedstartpulse.

A greater understanding of the pulsing sequence of counter system '70may be obtained from the following table. Each vertical column of thetable gives the output levels of the respective counters immediatelyafter the counter system receives the pulse named at the top of thecolumn.

An and circuit 76 has three inputs respectively connected to the outputsof counters #1, #2 and the rst output of #3. And circuit 76 provides anoutput b only when all inputs are at level LL initially, circuit 76 isdisabled bythe b level input received from counter #1.

A gate 77 receives the output of and circuit 76 at its `input 73.V Also,synchronous pulses-B are` applied to another input 42 of gate 77. Thus,gate 7'7 can pass a pulse-B only when allv inputs' of and circuit 7o areat level '71, which is seen' from the above table to occur only when adelayed-start pulse is received by counter system '70.

A decision iiip-i'iop circuit 82 is set according to whether a puise Aor B occurs first after a delayed-start pulse. An input 84 of flip-flop82 is connected to the output of gate 77 and another input 83 isconnected to the second output of counter #3. Flip-op circuit 62provides the output levels shown in Figure 4 immediately before adelayed-start pulse, because of the output states of the counters thenexisting. A pulse of b level at input 83 assures these preset outputlevels.

Consequently, as soon as al code-character start pulse is received atterminal Sil it is received by delay means 7i, which provides adelayed-start pulse one-quarter baud later to trigger counter #4. Then,counter #4 provides output level b, which simultaneously enables gate 72and triggers counter #l to provide output level a." Accordingly, anccircuit 76 receives levels a at all inputs to enable gate 77. However,gate 77 is enabled only until the first pulse-A occurs after thedelayedstart pulse, and it is only while enabled that a pulse-B can passthrough gate 77 to trigger ip-op $2. Hence, if a pulse-A occurs before apulse-B, gate 77 is closed before a pulse-B can trigger decision hip-hop82; and it continues to provide its normal outputs shown in Figure 4,which enable gate o2 and disable gate 63 of switching means 36. Thestored data from device 37 is then selected by switching means 36.

On the other hand, if a pulse-B occurs before any pulse-A after gate 77is enabled, the pulse-B triggers decision flip-hop S2 to reverse itsoutput states from those illustrated. Consequently, gate 62 is disabledand gate 63 is enabled, so that the direct non-synchronous input isselected by switching means 35. The first pulse-A follows shortlythereafter to trigger counter #l and disable gate 77, so that laterpulses-B cannot trigger flipfiop 82, until gate 77 is again enabled atthe beginning of the next code-character.

lt can be observed from the above table that counter #4 provides level boutput until the seventh pulse-A, when the system reverts to the initialnormal state in preparation for receiving the next code character.However, if decision flip-hop 82 is not then at the normal illustratedoutput levels, the transition of counter #3 after the seventh pulse-Acauses Hip-flop 32 to be triggered to the illustrated output levels.

Read-out gate d3 has an input S7 connected to output 4% yof switchingmeans 36. The synchronous pulses-B are provided at the other input ofgate 45 through a delay means Si) that delays pulses-B suiciently toprevent any coincidence between a sampling pulse-B and the operation ofgates o2 and 63. Thus, input 87 receives either the stored or the directdata as determined by storage device 37. Thus, gate 43 provides outputpulses synchronous with pulses-B and having voltage levels correspondingto that of the data.

A read-out ip-ilop 44 has its input StZ connected to the output of gate43. The output level of readoutv ipiiop 44 is triggered to a levelcorresponding to that of the received pulses and is provided to outputterminal 45 as a synchronous rendition of the nonsynchronous datareceived at input terminal 30.

Figure 5 illustrates timing sequences to aid an understanding of theinvention. Figure 5(A) shows a sequence of three nonsynchronouscode-characters itil, 162 and w3. Figure 5(3) illustrates thecorresponding delayedstart pulses 3.634, lob and litio provided by delaymeans 7i, which are about one-quarter baud behind the beginning of thecorresponding start (ST.) pulses of Figure 5(A).

Figures 5 (C) and (D) illustrate interleaved synchronous pulses A and Brespectively. Figure 5 (E) shows the stored (delayed) information fromtrigger' circuit y56. Note that the-*leading -edge-ofeach of stored'baudso Figure (E) aligns time-Wise with pulses-A. This is obvious fromthe structure of device 37 which is enabled by the data but is triggeredby pulses-A. Figure 5 (F) illustrates the synchronous output at terminal4S. Figure 5(G) illustrates an alternate readout that is permissible inregard to code character 163 of Figure S(A). Note that the read-outbauds all have their leading and trailing edges aligned with pulses-B(neglecting any delay by circuit 50). This is apparent from thestructure of read-out sampling circuit 43, wherein the output of thesystem is always triggered by pulses-B in gate 43.

Now considering nonsynchronous code character li in Figure 5(A) as beingreceived at terminal Sti, delayed# start pulse lili. is provided fromcircuit 7l one-quarter baud after the leading edge of its start pulse.Pulse 16M triggers counter #4 to enable gate 72 permitting pulses-A topass, and to simultaneously enable and circuit 76 permitting pulses-B topass. Thus, gates 72 and '77 are simultaneously enabled one-quarter baudafter the initiation of a code character. it can be seen from Figures5(C) and (D) that a pulse-A occurs lirst after delayed-start pulse i434.This pulse-A passes through gate 72, triggers counter #l to provide itwith a b level output which disables and circuit 76 and therefore gate'77. Consequently, decision iiip-op 82 remains in its initial outputstates (illustrated), which cause switching means 36 to select storeddata Vfor sarn pling by the read-out gate and flip-flop.

It is noted from the illustrated time relationship between Figures 5(A)and (C) that the pulses-A occur during the fty percent midportions ofthe bauds of character itil. Hence, storage gate 5l is sampling and istriggering ilip-llop 56 with the prime portions of the nonsynchronousincoming data. As a result, stored character liti in Figure 5(E) isdetermined to be optimum before being applied to read-out sampling gate43. lt will be noted from the time relationship between Figures 5(D) and(E) that pulses-B sample the midi-part of each of the bauds of storedcharacter Itiii. to provide readout character 101".

At the end of code character itil, a stop (SP.) pulse is received and isstored in ip-op S by the seventh pulse-A occurring after delayed-startpulse 104. Seventh pulse-A causes counter system 70 to reset to itsnormal state which disables gate '72 to prevent further actuation of thecounter system until after the next nonsynchronous code character 102 inFigure 5(A) is received. After the stop pulse begins, a teletypewritermachine continues to provide the same level as the stop puise until thenext code character has begun, which in effect extends the stop pulse.

As the next code character 5.62 begins, delayed-start pulse 165 inFigure 5(B) results one-quarter baud later. AS explained above, pulselil causes gates 72 and i7 to be enabled. However, it is observed fromthe timing of Figures 5(A), (C) and (D) that a pulse-B is passed by gate77 before it is disabled by a pulse-A. Hence, Hip-flop 82 is triggeredto opposite output states, whereby switching means 36 passes the directnonsynchronous data from terminal 3i? to sampling gate 43. Accordingly,read-out gate 43 directly samples the fifty percent midportions of thedirect data, as can be seen by comparing the timing of Figures 5(A) and(D). The resultant output from flip-op 44 is code-character 102 shown inFigure 5(F). At the end of the seventh pulse-A from the start ofcharacter 162, counter #3 triggers lipflop S2 back to its normal state,which enables switching means 36 to pass the stored data, if any exists.

Y it is noted during the direct read-out of character 62 that the storedinformation is not optimum in quality due to the timing of pulses-A withrespect to the input data. Accordingly, the stored data is not used bythe system when it may be erroneous.

After termination of code character 162 and. a nonsynchronous pause, thefollowing nonsynchronous code V8 character 103 starts and providesdelayed-start pulse 106 at one-quarter baud period later. The samesequence of events occurs as explained except that, as can be seen fromFigures 5(C) and (D), a pulse-B occurs simultaneously with delayed-startpulse N6. Due to such coincidence, it cannot be certain whether or notthe pulse- B can pass through gate 77 as it is being enabled. If

a suflicient portion of this pulse-B is passed to trigger flip-liop 82,the direct nonsynchronous input is sampled to provide read-out character103, illustrated in Figure 5(F), at terminal 46. On the other hand, ifthis pulse-B is not sufficiently passed through gate '77, the iirstpulse- A closes gate 77 so that flip-flop 82 is not triggered; andstored information is sampled instead to provide output character 103illustrated in Figure 5(G), at terminal 45. The point being made here isthat it basically makes no difference in the invention whether or not asynchronous pulse A or B coincides with' a start pulse, since the samequality of sampling is accomplished in either case, which is at theboundaries of the iifty percent midportions.

Trigger circuits of almost any type can be used in the invention ascircuits 44, 56 and 82, such as various known types using vacuum tubes,transistors, relays, or fcrroresonant circuits. Transistor triggercircuits have been found particularly desirable in models of theinvention because of their small size and the power consumption,combined with a high degree of reliability. Figure 8 illustrates a knowntransistor trigger circuit that is particularly adaptable in theinvention. It performs a memory function and is sometimes called atoggle circuit. It includes two transistors 210 and 2M having theiremitters connected by a common lead 213, which is connected to groundthrough a resistor 2l4 and a capacitor 215. A first parallel RC circuit217 connects the collector of transistor 2l@ to the base of transistor2li; and a second parallel RC circuit 21d connects the collector oftransistor 211 to the base of transistor 210. Resistors 221 and 222respectively connect the collectors of the transistors to a B- powersource. First and second trigger-circuit outputs are obtainedrespectively from the collectors of the transistors. A pair or" inputterminals 228 and 229 receive data to be retained by the circuit. A pairof differentiating capacitors 233 and 234 are serially connected toterminals 223 and 229. Also, a pair of diodes 226 and 227 have theircathodes respectively connected to the base of transistors 210 and 2liand have their anodes connected respectively to rst and secondcapacitors 233 and 23d. Further, a pair of resistors 231 and 232 arerespectively connected between the anodes of the diodes andcommon-emitterlead 213 to establish the bias on the diodes. Thecommonemitter lead 21.3 maintains at a substantially constant voltagedue tothe alternate operation of the transistors and therefore can beused as a voltage reference.

n vibrator which is referred to later in a discussion of Figure 6.Basically, it is a transistorized version of a well-known multivibrator.it includes transistors 311 and M2, which are biased between B- and B+power sources by resistors 316 through 32h. input triggering pulses ofpositive polarity are provided from terminal 321 through a capacitor 322to the collector of transistor 312. The Vduration of output pulsesprovided by the multivibrator is controlled by the time-constant ofcapacitor 322 and resistor 31S. This output pulse-length is adjusted toone-quarter baud period at the synchronous rate of pulses-B. Diodes 331,332 and 333 assist the pulsing operation within the multivibrator.

Figure 6 illustrates another form of the invention which uses triggercircuits of the type shown in Figure 8, which can be triggered only byinput pulses having a given polarity. Nevertheless, Figure 6 operates inbasically the same manner as Figure 4.

In Figure 6, nonsynchronous data is similarly received at terminal andis iirst passed through a low-pass filter 111 to attentuatehigh-frequency noise pulses. It is then passed through a pulse-Shaperand inverter 112 which squares the received pulses and providesoppositepolarity outputs, designated as 1 (inverted) and U (uninverted).Such iilters and pulse-Shapers are well known in the art and will not beexplained in detail herein.

Accordingly, an input baud mark will have a positive polarity in onlyone channel, such as provided by uninverted output (U), and an inputbaud space will have a positive polarity only in the inverted channelprovided by output (I). In general, the trigger circuits of Figure 6 arepresumed to be responsive only to positive polarity input pulses.

The synchronous-timing waves A and B used in Figure 6 do not haveprecisely the same form as previously given for pulses A and B. Figure7(A) illustrates synchronous timing wave-A; and Figure 7(1) illustratessynchronous timing wave-B. These waves have a fifty-percent duty cycle,with wave B being polarity inverted with respect to wave A. The positivetransitions of each of waves A and B correspond in time to pulses A andB, respectively, given in Figures (C) and 5 (D). When either of thesewaves is provided through a differentiating circuit, comprising acapacitor and resistor having a short-time constant, positive pulses Aand B are respectively provided. As a practical matter, capacitors aregenerally needed at the inputs to various parts of the system in orderto maintain proper bias levels. It is generally simple to have suchcapacitors and associated resistances act as differentiating circuits toderive the required pulses A and B. Thus, in storage device 37 in Figure6 dierentiating circuits 113 and 114 are provided and are connected towave-A at terminal 35. Their outputs provided pulses-A to inputs ofrespective gates 51a and 51b.

The inverted output (I) and an uninverted output (U) of pulse-Shaper 112are also respectively received by gates 51a and 5112. The two inputs 57aand 57b of storage fliplop 56 are connected respectively to the outputsof gates 51a and 5111; which are respectively enabled only when theyreceive positive polarity inputs. Consequently, only the gate which isreceiving a positive data baud is enabled. For example, gate 51a isenabled only by baud spaces, and gate 51b is enabled only by baud marksAs a result, ip-tiop S6 is triggered by its two inputs to an outputstate that corresponds to the received data.

Switching means 36 is the same as given in Figure 4 in regard to gates62 and 63, and or circuit 66. Means 36 only handles uninverted (U) data,since gate 62 receives the uninverted output of flip-op 56 and gate 63receives the uninverted output of Shaper 112. However, to assist theoperation of later flip-dop circuits, switching means 36 in Figure 6includes an inverter 116 connected to or circuit 66. Thus, switch 36provides outputs U and I.

Read-out sampling gates 43a and b respectively received the invertedsignals U and I from switching means 36. Gates 43o and b aresequentially enabled by the signal that has positive polarity during agiven baud period. They also receive pulses-B at their other inputs fromditterentiating circuits 118g and b connected to synchronous wave-B.Hence, gate 43a provides a pulsed output only for data marksf and gate43h only for data spaces The inputs 92a and b of read-out nip-flopcircuit 44 are respectively connected to the outputs of gates 43a and43h. Flip-hop 44 is triggered according-ly to provide the synchronousdata, as explained above.

in Figure 6, which are connected to the respective outputs of ip-opcircuit 44, provides the synchronous output data, one output beingpolarity inverted with respect to the other.

The input to decision device 38 in Figure 6 is connected to the output Uof pulse-Shaper 112. In Figure 6, delay means 71 is also a coincidencecircuit, which not only causes a quarter-baud delay, but alsodiscriminatesv against unwanted noise pulses. Delay means 71 comprises adifferentiation circuit 121 that receives the nonsynchronous data. Aone-shot multivibrator 112, which can be that shown in Figure 9, isconnected to the outputr of differentiating circuit 121. Whenevertriggered, oneshot multivibrator 122 is actuated for a period equal toone-quarter of a baud period. Another differentiating circuit 123receives the output of multivibrator 122. A gate 124 has an inputconnected to differentiation circuit 123, but has another input 126connected to the output U of pulse-Shaper 112 to receive' directly thenonsynchronous data. Hence, whenever a code-character begins, theleading edge of its start pulse acts through differentiating circuit 121to trigger multivibrator 122. After one-quarter baud'period,multivibrator 122 reverts to its original state, and in the transitioncauses a pulse through differentiating circuit 123 to gate 124, which isbeing enabled by the start pulse. Thus, the pulse passes through gate124 and triggers counter #4 of counter system 70. Therefore, acoincidence between the start pulse and the delayed output ofmultivibrator 122 must exist to provide an output from delay means 71.Noise pulses may trigger multivibrator 122; but if no start pulseexists, gate 124 will be closed' to prevent any output from means 71.

The operation or" counter system 76, gate 72, and circuit 76, gate 77,and decision flip-flop 32 is the same aS explained in connection withFigure 4. The counters #1*#4 in system 7i) can each be made similarly tothe circuit illustrated in Figure 8, except inl Figure 8 more detailisshown in regard to input-output connections of the component counters,with differentiation circuits provided between them to assisttriggering. Synchronous pulses-A are provided to gate 72 from adifferentiating circuit 115 that receives synchronous wave-A fromterminal 35. Also, a differentiating circuit 116 is connected betweenthe output of counter #4 and an input to counter #l to improvetriggering action.

Another differentiating circuit 131 is interposed between wave-Bterminal 46 and gate 77 to provide pulses- B to gate 77. Further, adifferentiating circuit 132 is connected between input 84 of llip-op 82and the output of counter #3 to improve triggering action.

An additional feature that eliminates a potential ambiguity in thesystem is provided in Figure 6, and replaces the operation of delay line50 in Figure 4. In Figure 6, this feature is provided by adifferentiation circuit 144 connected to a gate 141. Circuit 144 has itsinput connected to output u of decision flip-flop 82. Gate 141 has anenabling input 142 connected to the output of and circuit 76, and theoutput of gate 141 is connected to input 92a of read-out tiip-flop 44.The resolved ambiguity occurs when direct-data sampling is done by thesystem. In such case, a sampling-pulse-B arrives at read-out gates 43aand b at about the same time as the direct data is switched to theoutput of switching means 36. This situation is caused by decision ip-op82 being triggered by a pulse-B at the same time as readout gate 43receives a pulse-B. Consequently, gate 63 opens to pass the direct inputdata to sampling gates'43a and b in the read-out circuit at the sametime that a sampling pulse-B is received by gates 43a and b. Hence, itis unlikely that gate 63 can be opened fast enough to permit the directdata to be sampled bythe pulse-B applied to gates 43a and b.Accordingly, the start pulse'data of a character may be missed;although, of course, gates 63 '11 will be enabled during the remainingbands of the character to permit them to be read-out accurately.

In Figure 6, whenever a pulse-B actuates flip-flop 82, the switchedoutput at terminal 35a causes a. pulse through diferentiating circuit144 and gate M1, which is enabled at this time by the output from andcircuit 76, to trigger a mark output from read-out circuit 44, whichprovides the required start baud. The start baud, by definition, alwaysis identified by the same electrical quantity (which is herein the sameas a inarlc). The operation of Figure 6 is further explained usingFigures 7(A-L). A numbered time-base t is illustrated across the top ofthe sheet and is common to ail of its figures. Figure 7(A) illustratestiming wave-A. Figure 7(B) provides a nonsynchronous sequence ofteletypewriter data which represents the Word ANY. The seven bauds ofeach character are bracketed to identify the letter they respectivelyrepresent. Adjacent bauds of the same polarity are run together in theconventional manner.

Consider first the start pulse (ST.) of the character representing theletter A. At the initiation of its start pulse, one-shot multivibrator122 is triggered to provide a pulse 151 in Figure 7(C) having a durationequal to one-quarter baud period. The trailing edge of multivibratorpulse 151 is positive-going and provides a positive pulse at the outputof differentiating circuit E23 which passes through gate 124, since itis being enabled at input 126 by the existing start pulse. The pulsefrom gate 12d triggers counter #4 to provide output level b asillustrated by pulse 161 to Figure 7(B). The leading edge of' pulse 161from counter #4 causes a pulse from ditferentiating circuit 116 thattriggers counter #l to provide output pulse 171 given in Figure 7( E),which is at level a. Simultaneously, gate 72 receives level b pulse 161from counter #4 and is enabled for the reception of pulses-A.

During the period of counter #l pulse 171, and circuit 76 is enabled toprovide output pulse 181, illustrated in Figure 7(H). Pulse 131 from andcircuit 7d enables gate 77 for the reception of a pulse-B. However, fromFigures 7(A) and (J), it is noted that a positive transition of timingwave-A thereafter occurs before a positive transition of timing wave-B.Accordingly, a pulse-A is first provided and passes through gate 72 totrigger counter #l back to level b, which terminates pulse 171illustrated in Figure 7(B) and pulse 181 in Figure 7(H). However,counter #4 continues the b level output, thus continuing to enable gate72 for the reception of pulses-A. Figures 7(B). (F) and (G) illustrateby means of pulses 171, 191 and 201 the actuations of counters #1, #2and #3 during the reception of the first seven pulses-A. The seventhpulse-A after the beginning of character A reverts counter #4 to alevel, preparing it for the next data character.

Figurei7(l) represents the output of decision device 3E which controlsswitching means 36. The first Voccurrence of a pulse-A for firstVcharacter A caused device Si; to decide that switching means 36 shouldcontinue to pass stored data. The stored data is illustrated in Figure7(K). Hence, the positive transitions (pulses-B) of wave-B in Figure7(1) sample the stored data of character A in Figure 7(K) to actuateread-out circuit 44', which accordingly provides synchronous outputcharacter A, shown in Figure 7 (L).

During the information bauds of nonsynchronous character A in Figure7(B), the positive-going baud transition 222 caused a pulse 152 fromone-shot multivibrator 122 while gate 12d was enabled to provide anoutput from delay means 71. However, this output cannot actuate counter#4, since it is at level b during the five information bauds.

The next character provides the letter N. lts start baud similarlyactuates the system in the same manner as explained for the letter A toenable gates 72 and 77.

However, due to the different phasing of character N,

a positive transition of the timing wave-B occurs first and triggersdecision fiip-fiop S2. Accordingly, switching means 36 reverses, asshown by pulse 211 in Figure 7(1) to pass the direct nonsynchronous datato read-out sampling gates 43a and b. Also, the transition of dip-flop82 causes a pulse from differentiating circuit 144 that passes throughgate 141, which is enabled at this time by and circuit output pulse 182in Figure 7(H), to trigger input 92a of the read-out Hip-flop t4 andprovide a synchronous output start pulse.

Thereafter, the system output provides synchronous character N in thesame manner as previously described for character A, except that thedirect input of Figure 7(B) is sampled by the positive-transitions ofwave-B in Figure 7(1). Further, it is noted that the seventhpositive-transition of wave-A (seventh pulse-A) after the beginning ofcharacter N results in a triggering of counter #3 at 203, wherein itsfirst output causes a pulse from differentiating circuit 132 to input S4of decision fiip-flop 82 to reverse its output state, and thus permitstored data to again pass through switching means 36.

Similarly, the character Y actuates the system in the same manner asexplained for character A, except that its information bauds aredifferent. However, this is automatically treated by the system.

it is noted in Figure 7 that the character periods of the nonsynchronousdata average to be longer than the character periods of the synchronousoutput. Hence, when the nonsynchronous data is continuous, theregenerally will be excess time in the synchronous output. This excesstime is accounted for by occasionally doubling the period of asynchronous stop pulse such as stop pulse 231 in Figure 7(L), which doesnot interfere with the synchronism of the output.

Although this invention has been described with respect to particularembodiments thereof, it is not to be so limited as changes andmodications can be made therein which are within the full intended scopeof the invention as defined by the appended claims.

i claim:

l. Means for converting nonsynchronous binary data to synchronous data,comprising a bistable-storage device enabled by said nonsynchronousdata, a source of synchronous A-pulses connected to said storage deviceto sample said input data at the synchronous rate of said A-pulses, adecision device connected to receive the nonsynchronous input and beingalso connected to said A- pulse source, a synchronous source of B-pulsesphased degrees with said A-pulses and connected to said decision device,said decision device measuring the phasing of the A-pulses and B-pulsesrelative to the mid-portions of the received binary data, switchingmeans having inputs connected to the nonsynchronous input and to thesyn` chronous output of the storage' device, said switchingmeansselecting one of its inputs at one time for its output, saiddecision device connected to said switching means to control its outputselection, said switching means se'- lecting its storage-device inputwhen said decision device measures the'phase of said A-pulse occurrenceduring the general mid-portions of said nonsynchronous binary data, andsaid switching means selecting its nonsynchronous input when saiddecision device measures the phase of said B-pulse occurrence during thegeneral mid-portions of said nons'ynchronous binary data, a read-outsampling gate being connected to the output of said switching mean andtol synchronously sample the selected data.

2. Means for converting nonsynchronous teletypewriter baud-charactersreceived at at input terminal to a synchronousroutput, comprisingstorage means connected to said terminal for delaying said input byabout one-half a band,'a source of synchronous A-pulses, and a source ofsynchronous B-pulses occurring midway between said A- puls'es, switchingmeans having one input connected to the output of vsaid storage meansand having another input 13 connected to said' input terminal, saidYswitching means" connecting either one or the other of its inputs to itsoutput, ardecision-control device having a data input connected to saidinput terminal, av plurality of gate means in said decision deviceconnected to said A and B pulse sources', said gate means being enabledby the start of each of said characters, one of said gate means beingdisabled by the lirst A-pulse received after being enabled, a bistabledevice being connected to the output of said one gate means, said onegate means passing any B-pulse occurring while enabled to trigger saidbistable device, the output of said bistable device being connected tosaid switching means to control its switching state, with said switchingmeans normally connecting the output of said storage means Ato itsoutput, said normal connection being reversed when said bistable deviceis triggered by a B-pulse, baud-counting means being included in saiddecision device to trigger said bistable circuit to its normal state atthe end of each character, a read-out bistable gate having an enablinginput connected to the output of said switching means, and

said source of B-pulses connected to said read-out gate to synchronouslysample the data received from said switching means.

3. Means for converting nonsynchronous input baudcharacters to asynchronous output comprising, a source of synchronous A-pulses, and asource of B-pulses, with said B-pulses occurring midway between saidA-pulses, a synchronously-enabled bistable-storage device having aninput receiving said nonsynchronous baud-characters, the output of saidbistable-storage device being timed with said A-pulses, double-throwswitching means having one input connected to the output of saidbistable-storage device and having another input receiving saidnonsynchronous baudcharacters, a decision device includingonequarter-baud delay means receiving said nonsynchronousbaudcharacters, first and second and gates in said decision devicerespectively connected to said sources of A-pulses and B-pulses, acounter system in said decision device being connected to said delaymeans and being started by the beginning of a delayed character toenable said iirst and second gates, said second gate being disabled bythe first A-pul'se received after being enabled, a decision ip-op beingconnected to the output of said second gate and being triggered by aB-pulse passing through said gate, a control input of said switchingmeans being connected to said decision hip-nop with the switchedposition olf said switching means corresponding to the output state ofsaid decisionip-op, said counter system being connected to said decisionip-op to trigger it to a normal state at the end of each inputcharacter, a read-out gate having an input connected to the output ofsaid switching means, said source of B-pulses being connected to saidread-out gate to synchronously sample the output received from` saidswitching means.

A nonsynchronons to synchronous converter receiving inputnonsynchron'ous teletypewriter baud characters, comprising a storagedevice, including a gate, and a stor'- age flip-nop; with an enablinginput ot said gate receiving said nonsynchronous bauds, a source ofsynchronous A' pulses connected to said gate to synchronously samplenonsynchronous bauds', with the output of said gate being connected tosaid storage flip-op to correspondingly trigger it synchronously to thebinary state of the received nonsynchronous input;V a double-throwswitching means having one input connected to the output of said storageilip-iiop, and having itsother input receiving said input nonsynchronousbauds; `a read-out circuit having/a 'readout gate, and 'a readouthip-dop, with said read-'out gate having an enabling input connected tothe output of said switching means, a source of synchronous B-pulsestimeinterleaved with said A-pulses, means connecting said B- 'uise source tosaid read-out gate, with the output of'said read-out gate triggeringcorresponding output states of said read-'out iiipliop; a decisiondevice including, al quarteru's'a'ud deiay means having'y its inputreceiving said input' nonsynchronus bauds, iirstv and second controlgates with the'fir'st control gate being connected to said? source ofA-pulses and the second control: gate being cori-f nected tosaicl'source'of B-pulses, means for enabling both of said control gatesin response to a character-start output from said" quarterbaud delaymeans, a decision ipop having an inputI connected to the output of thesecond control gate', disablingfmeans' connected between the output `ofsaid rst control gate and an input o' said second controll gate,` withsaid disablingv means being actuated by anyl A-pulserpassing throughvsaid rst control gate to disable said second control gate, said secondcontrol gate while enabled being capable of passing a B-pulse to triggersaid decision flip-Hop, said switching means being connected to theoutput of said decision flip-flop and being actuated according to theoutput state of said decision flip-dop, and said disabling meansproviding a reset pulse to said decision ip-op near the end of eachquarter-baud delayed character.

5 .p Converter means as defined in claim 4 in which said disabling meanscomprises a counter system having a plurality of counters with theoutput of one of the counters bei-ng connected t`o` the enabling inputof said rst cont-rol gate, an andfci'rcuit having a plurality of inputscoupled! to outputs of at least some or said counters, the output ofsaidlqua'rter-baud delay means being connected t'o the input of one ofsaid counters, and an enabling input of'said second control gate beingconnected to the output of' said and circuit.

6. Means for converting a nonsynchronous baud-character input intosynchronous output data, comprising a source of A-pulses, and a sourceoi B-pulses, with said pulses being synchronous vand said B-pulseshaving a degree phase relationship with said A-pulses, a storage gatereceiving the nonsynchron'ous input characters at an enabling input andhaving another input receiving said A-pulses to synchronously samplesaid nonsynchronous bauds, a storageviplop receiving the output of saidstorage gate and being synchronously triggered to corresponding outputstates, double-throw switching means having one input connected to theoutput of said storage flip-hop and having another input receiving saidnonsynehronous characters, a read-out gate having an enabling inputconnected to the output of said switching means and another inputconnected to said Bpulse` source to synchronously sample data receivedfrom said switching means, a readout ip-op receiving the output of saidread-out gate and having its output correspondingly triggered to providesynchronous output data; a decision device including, quarter-baud delaymeans receiving said nou-synchronous input, a counter system having atleast first-second, third and fourth tandem-connected binary counters,with an input to the fourth counter connected to the output of saiddelaymeans, a first control gate having anv enabling input connected tothe output of the fourth counter and having another input receiving saidA-pulscs and having an output connected to an input of the rst counter,an and circuit having inputs connected to outputs oi iiret, second andthird counters, said and circuit being enabled by said counter systemupon the start or a quarter-baud delayed character from said delaymeans, a second control gate having anv enabling input connected to theoutput of said and circuit and having another input receiving saidB-pulse source, a decision tiip-op having an input connected to theoutput of said second control gate, means connecting the output of saiddecision flip-nop to said switching means, with the state of saidswitching means being controlled by 'opposite state of flip-dep.

7. A nonsynchronous to synchronous converter as deiined in claim 6 inwhich the input to said decision flipiiop is connected to the output ofsaid third counter to trigger said decision dip-flop at the end of acode character to a normal voutput state, said normal output statecausing lsaid switching means to pass to its input' from said storagedevice.`

15 8. A nonsynchronous to synchronous converter means as defined inclaim 7 having means connecting the output of said decision dip-flopdirectly to the input to said readout tiip-fiop, with actuation of saidfiip-tiop from a normal output state triggering said read-out flip-fiop.

9. A nonsynchronous to synchronous code converter as ydefined in claim 7in which said switching means comprises first and second switchinggates, with each having enabling inputs respectively connected to theoutput of' said storage flip-flop and to the nonsynchronous input ofsaid converter, said decision flip-dop providing a pair of oppositeoutputs respectively connected to other inputs of said first and secondswitching gates, with the normal output state of said decision tiip-flopmaintaining said first gate enabled to pass the output of said storagefiipflop, an or gate having a pair of inputs respectively connected tothe outputs of said first and second switching gates, and the output ofsaid or circuit connected to an input of said read-out gate.

10, Means for converting input nonsynchronous character-coded bauds tosynchronous bauds, with each character introduced by a start pulse,comprising sources of A-pulses and B-pulses which are synchronous andtime-interleaved, a delay device receiving the nonsynchronous startpulses and providing an output pulse one-quarter baud period after thebeginning of each start pulse, a counter system having a plurality ofbinary counters connected in tandem and being able to count up to atleast the number of bauds in each of said code characters, with the lastof said counters having an input connected to the output of said delaydevice, a first control gate having inputs connected to the A-pulsesource and to the output of the last counter, said first control gatehaving its output connected to the input of the first counter, saidfirst control gate being enabled by the last counter upon its receptionof an output pulse from said delay device, an and" circuit having aplurality of inputs connected to outputs of several of said counters,said and circuit being enabled upon reception of a delayed start pulsefrom said delay device by said fourth counter, said and circuit havingits output disabled by said first A-pulse passing through said firstcontrol gate, a second control gate having an enabling input connectedto the output of said and circuit and having another input connected tosaid B-pulse source, a decision flip-flop having a first input connectedto the output of said second control gate and having a second inputconnected to an output of the next-tolast counter for resetting saiddecision filip-flop to a normal output state, a storage-gating meanshaving an input receiving said nonsynchronous bauds and having anotherinput receiving said A-pulses to sample said bauds at the rate of saidA-pulses, a storage liip-fiop being triggered by the output of saidstorage gating means, first and sccond switching gate means, with theinput of said first switching gate means being connected to the outputof said storage flip-flop, and with the output of said second switchinggate means receiving said nonsynchronous input bauds, an or circuithaving inputs connected respectively to the outputs of said first and`second switching gate means, said first and second switching gate meanshaving triggering inputs respectively connected t 16 gate having aninput also receiving said nonsynchronous input bauds, a seconddifferentiating means connected between the output of said multivibratorand another input to said and gate, and the output of said and gateconnected to the inputV of the last counter.

12. A nonsynchronous to synchronous converter as defined in claim 10 inwhich said counter system has four binary counters, whereby said countersystem accommodates teletypewriter characters, each having fiveinformation baud periods in addition to stop and start pulses.

13. A nonsynchronous to synchronous converter means `as defined in claiml0 including triggering means coupled between an output of said decisionflip-flop and the input to said read-out Hip-flop to automaticallytrigger its output to a level corresponding to a synchronous outputstart pulse after an input start pulse is received.

14. A system as defined in claim 13 in which each ipfiop is actuatableto opposite states by pulses having the same polarity but provided atopposite inputs, a first inverter receiving said nonsynchronous inputand providing opposite-phased outputs, said storage-gating meanscomprising a pair of gates respectively connected between the oppositeoutputs of said inverter and the opposite inputs of said storageflip-flop, a second inverter connected to the outputs of said first andsecond switching means, said read-out gate means comprising a pair ofread-out gates, with said read-out gates being connected respectivelybetween opposite-phased outputs from switching gate means and theopposite inputs of said read-outl flip-dop.

15. A means for converting a nonsynchronous teletypewriter signal to asynchronous signal, with each teletypewriter character having a startpulse, five information bands and a stop" baud, comprising a pulseshaperreceiving said nonsynchronous signal and providing inverted anduninverted outputs, a delay multivibrator providing a one-quarter bauddelay having its input connected to one output of said pulse-Shaper, acounter system having four binary counters connected in tandem, with theinput to the fourth counter being connected to the output of said delaymultivibrator, a synchronous timing source providing invertedsquare-waves opposite outputs of said decision fiip-fiop, read-out gateA and B, a first control gate having an output connected to an input ofsaid first counter, differentiating means connected between the outputof said fourth counter and the input of said first counter, A-wavedifferentiating means generating positive A-pulses, and B-wavedifferentiating means providing positive B-pulses, said A-pulsesprovided to one input of said first Vcontrol means, another input ofsaid first control gate connected to the output of the fourth counter,an and" circuit having inputs respectively connected to the outputs ofthe first, second, and third counters and being enabled by the receptionof a first pulse from said delay multivibrator per-code-character, adecision ip-iiop having a pair of `nputsand a pair of inverted outputs,a second control gate having an input connected to the output of saidand circuit and an output connected to an input of said decisiondip-flop, the differentiating means for said B- wave connected to theother input of said second control gate, another difierentiating circuitconnecting another output of said third counter to an opposite input ofsaid decision flip-flop; a storage fiip-flop having a pair of inputs andan output, a pair of storage gates having their outputs respectivelyconnected to the inputs of said storage flip-dop, respective inputs ofsaid storage gates connected to the opposite inverter outputs of saidpulseshaper, said storage gates receiving the differentiated A- wave,first and second switching gates, with the first switching gate havingan input connected to the output of said storage dip-dop, said seconddecision gale having an enabling input connected to an output ofcorrespondinglyopposite polarity of said pulse-Shaper, the first andsecond switching gates having other inputs respectively connected to theopposite output of said decision tiip-fiop, an or circuit having itsinputs connected to the outputs of said switching gates, first andsecond read-out gates, with said first read-out gate having an inputconnected to the output of said or circuit, a polarity inverterconnected between the output of said or circuit and an input of saidsecond read-out gate, other respective inputs of said first and secondread-out gates receiving the differentiated B-wave, a read-out fiip-flophaving a pair of opposite inputsprespective'ly connected to the outputsof said read-out gates, a start gate having its output connected to oneinput of said read-out fiip-op and having one input connected to theoutput of said and circuit, and a third differentiating circuitconnected between an output of said decision fiip-tiop and another inputto said start gate, with said read-out flip-dop providing thesynchronous output of said system.

16. A system for converting nonsynchronous binarycoded input charactersinto a baud-synchronous output, wherein a plurality of binary bauds areincluded in each character, comprising means for splitting said inputcharacters into at least two channels, means for delaying one channelbehind the other channel by approximately one-half baud, means providingat least first and second sets of synchronous timing pulses, said setsbeing time interleaved, means for sensing the start of each inputcharacter and providing a sense pulse delayed by approximatelyone-quarter baud behind each start, means for determining which of saidsets provides a first pulse after sense pulse and providing a first orsecond output according to which set occurred first, switching means forselecting one of said channels as its output corresponding to arespective output of said determining means, sampling means connected tothe output of said switching means for sampling its output insynchronism with the timing of said sets.

17. A system for converting input nonsynchronous lbinary data charactersto baud-synchronous data characters comprising, means for splitting saidinput characters into at least first and second paths, a first sourceproviding a first set of synchronous-timing pulses, and a second sourceproviding a second set of synchronoustiming pulses, with the pulses ofthe rst set occurring during the mid-periods of the pulses of saidsecond set, first sampling means for sampling the data of said firstpath with said first set, means for regenerating data sampled by saidfirst sampling means, means for providing a decision input signaldelayed behind a beginning of each character by about a quarter baud,decision means receiving said decision input signal and determiningwhich of said sets has a pulse occurring first after each decision inputsignal, switching means connected to the ouput of said regeneratingmeans and to an output of said first path to pass one of these outputsin response to a determination of said decision means and secondsampling means for sampling the passed output of said switching meanswith said second set.

18. A system for converting nonsynchronous input binary-coded datacharacters to baud-synchronous characters, comprising a source providingsets A and B of l synchronous pulses, with the pulses of set A delayedonehalf a baud behind pulses of set B, a first path having an output ofnonsynchronous input data, a second path receiving said input data andregenerating it in synchronism with set A, means for generating a pulsedelayed one-quarter baud behind a beginning of each input character, adecision means for determining which of said sets provides a first pulseafter said generated pulse, first or second outputs from said decisionmeans respectively provided for the first occurrence of set A or B,switching means receiving the outputs of said first and second paths andreceiving the first and second outputs of said decision means, saidswitching means passing said first path in response to the first outputof said decision means, said switching means passing said second path inresponse to the second output of said decision means, and outputsampling means connected to the output of said switching means andsampling it with said set B.

19. A means of converting nonsynchronous teletypewriter coded inputcharacters to baud-synchronous output characters, comprising a source ofA-pulses, and a source of B pulses, with said pulses being synchronousand being time-interleaved with respect to each other, means forsynchronously sampling the nonsynchronous input characters with saidA-pulses, a first bistable-storage device connected to said samplingmeans for storing bits of said sampled characters, means for generatingdecision input pulses delayed behind a beginning of each of saidnonsynchronous input characters by approximately one-quarter baudperiod; decision means, including decision gate means being enabled inresponse to each decision input pulse and having an input connected tosaid source of B pulses, a decision bistable circuit being reset inresponse to said A-pulses, said decision gate means having an outputconnected to a set input of said decision bistable circuit, means fordisabling said decision gate meansv with the first A pulse occurringafter its enablement, first and second switching gate means beingconnected to said decision bistable circuit which enables said firstgate when set and enables said second gate when reset, output samplinggate means connected to combined outputs of said first and secondswitching gate means, said output sampling gate means samplingsynchronously with said B pulses, and readout bistable means beingtriggered by said output sampling means to shape said synchronous outputsignal.

References Cited in the flle of this patent UNITED STATES PATENTS2,552,968 Hochwald May 15, 1951 2,596,147 Hampton May 13, 1952 2,843,669Six et al. July 15, 1958

